Defect_Detection_Hub

Simple, web based and pluggable Defect Detection Solution

One shot Defect Detection

In semiconductor manufacturing, defect management traditionally relies on a highly mechanical, two-step process of optical defect inspection followed by high-resolution SEM review. The traditional Die-to-Die review approach physically drives the SEM stage to a neighboring golden die to capture a second reference image for subtraction. This physical stage navigation creates a massive throughput bottleneck, capping review speeds at only several hundred defects per hour compared to the tens of thousands flagged by high-speed optical sweep tools. Shifting to a single-image non-reference defect detection paradigm completely eliminates secondary stage movements, instantly doubling the review capacity of multi-million dollar SEM fleets. Additionally, this reference-free methodology offers vital EUV resist protection by halving electron irradiation, which drastically minimizes stochastic damage on delicate sub-nanometer wafers.

General Approach

The unified single-image pipeline begins by classifying the topological structures of an incoming SEM view using high-speed cosine similarity maps. To achieve this, the image is partitioned into subimages to analyze regional structural details and isolate repeated topological features against adaptive thresholds. The geometric parameters of these regions are evaluated using specific criteria—such as axis ratios and connected component counts—to route the image to an optimal solver. For structured image types, the algorithm utilizes the internal structures to mathematically reconstruct a perfect, defect-free synthetic reference. Subtracting this synthetic background from the original input produces a clean, flattened image where the true defects spike through as outliers without requiring a physical reference die.

Cases

Flat images feature uniform or homogeneous backgrounds where anomalies are directly isolated by analyzing outlier deviations in the pixel intensity distribution. Linear images are characterized by dominant parallel circuit lines, which the routing engine classifies by calculating the dominant trajectory angle before mathematically removing them. Patterned images consist of highly repetitive arrays, allowing the system to extract precise lattice vectors to digitally average out background features into a synthetic reference. If an image lacks flat, linear, or periodic layouts, it is categorized as a complex image representing irregular logic geometries and non-repeating routing patterns. While flat, linear, and patterned topologies are resolved using deterministic, lightweight mathematical filters, complex cases are routed to a custom convolutional neural network.

Optimization

To optimize structural classification, the routing engine calculates the Jensen-Shannon Divergence between the image's intensity histogram and an estimated Gaussian distribution. For statistical modeling, the Minimum Covariance Determinant estimator is optimized to compute robust inlier distributions, ensuring that standard deviations are not skewed by the presence of large defects. Image preprocessing is optimized using Perona-Malik anisotropic diffusion to reduce high-frequency noise while preserving sharp boundaries and delicate textures. For complex logic structures, the deep learning pipeline utilizes a specialized neural network architecture optimized with residual block skip connections to maximize segmentation accuracy. Training for this segmentation network is optimized by combining boundary loss with adaptive generalized dice loss to overcome the extreme class imbalances of small defects on large chip backgrounds.

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