Hot_Spot_Hub
Simple, web based and pluggable Hot Spot and OPC optimization Solution
Hot_Spot_Hub
Hot Spot Hub is an interactive, GPU-accelerated Inverse Lithography Technology (ILT) and optical proximity correction (OPC) sandbox that bridges physical wafer metrology and advanced computational EDA. The platform automates GDSII layout ingestion, performs rapid optical failure hotspot extraction, and trains physics-informed neural surrogates (DeepONet and Fourier Neural Operators) to simulate scanner diffraction blur in milliseconds. By running real-time Manhattan and curvilinear mask optimization under manufacturing guardrails, the suite demonstrates quantifiable yield improvements, achieving up to a +8.72% net gain in Wafer Pattern Fidelity (IoU)
GDS Viewer
GDSII Layout Ingestion & Hotspot Analysis Direct parsing of raw GDSII files to automatically extract target design layers and identify high-risk manufacturing failure zones. The engine scans complex geometries to isolate critical hotspots—such as line pinching, bridging, and severe line-end pullback—where optical diffraction threatens physical circuit integrity before the layout ever hits the mask shop,
DeepONet and FNO training
Physics-Informed Deep Learning Surrogates Bypasses the computational bottleneck of classical wave-optics calculations (Hopkins TCC wave integration) using GPU-accelerated neural surrogates. By training DeepONet and Fourier Neural Operator (FNO) architectures on diverse synthetic semiconductor layouts, the platform functions as an ultra-fast, differentiable forward optical engine that predicts continuous aerial image light intensities in milliseconds.
OPC optimization
Hardware-Aware Inverse Lithography Technology (ILT) Compares rectilinear TV-regularized (Manhattan) spatial optimization against frequency-domain Fourier (Curvilinear) optimization to counteract light diffraction. To ensure the resulting organic, high-fidelity masks are actually manufacturable, the optimizer enforces Deep Core Locking and 5x5 Morphological Mask Rule Checks (MRC) to suppress unmanufacturable "chrome dust," ultimately expanding the process window and boosting Wafer Pattern Fidelity (IoU) by up to +8.72%.
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